FPGA2007: Preliminary Technical Program

Please send any errors or other issues to Mike Hutton.

Bolded author name is the presumed speaker.

Regular paper talks are 20 minutes, including time for questions. Poster sessions will begin with an overview of the posters by the session chair.

Sunday, February 18

Pre-Conference Workshop on Grand Challenges in FPGA Research
2:30pm	Session W1: High-level CAD and Architecture
2:40pm to 3:45pm	Jason Cong, UCLA
	Kurt Keutzer, UCB
	Grant Martin, Tensilica
	Discussion
3:45pm	Break
4:10pm	Session W2: Low-level CAD and Architecture
4:15pm to 5:30pm	Vaughn Betz, Altera
	Steve Trimberger, Xilinx
	Jonathan Rose, Toronto
	André DeHon, U.Penn
	Discussion
Reception
6pm	Registration
7pm	Opening Reception

Monday, February 19

Session 1: Architecture And Technology
8:40am	Opening Remarks
9:00am	A Routing Fabric for Monolithically Stacked 3D-FPGA Mingjie Lin and Abbas El Gamal Stanford University, California, CA, USA
	Design of a Logic Element for Implementing an Asynchronous FPGA Scott Smith University of Missouri – Rolla, MO, USA
	Designing Efficient Input Interconnect Block for LUT Clusters Using Counting and Entropy Wenyi Feng and Sinan Kaptanoglu Actel Corp., Mountain View, CA, USA
	A Synthesizable Datapath-Oriented Embedded FPGA Fabric Steven Wilton, Chun Hok Ho, Philip Leong, Wayne Luk and Brad Quinton Imperial College, London, UK and The University of British Columbia, Vancouver, Canada
10:20am	Poster Session 1
Session 2: Implementation and Emulation
11:15am	A versatile, low latency HyperTransport core David Slogsnat, Alexander Giese and Ulrich Bruening University of Mannheim, Germany
	An FPGA-Based Pentium(R) in a Complete Desktop System Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, and Michael Konow Intel Corp, USA; University of Toronto, Canada; and Georgia Tech, USA.
	A 1000-Word Vocabulary, Speaker-Independent, Continuous Live-Mode Speech Recognizer Implemented in a Single FPGA Edward Lin, Kai Yu, Rob Rutenbar and Tsuhan Chen Carnegie Mellon University, Pittsburgh, PA, USA
12:15pm	Lunch
Session 3: CAD
2pm	Variation-Aware Routing for FPGAs Satish Sivaswamy and Kia Bazargan University of Minnesota, Minneapolis, MI, USA
	Stochastic Physical Synthesis for FPGAs with Pre-routing Interconnect Uncertainty and Process Variation Yan Lin and Lei He University of California at Los Angeles, CA, USA
	Post-Route LUT Output Polarity Selection for Timing Optimization Kai Zhu Actel Corp, Mountain View, CA, USA
3pm	Poster Session 2
Session 4: FPGA-based Computing
4pm	Synthesis of an Application-Specific Soft Multiprocessor System Jason Cong, Guoling Han and Wei Jiang University of California, Los Angeles, CA, USA
	FPGA-friendly Code Compression Technique for Horizontal Microcoded Custom IPs Bita Gorjiara and Daniel Gajski University of California, Irvine, CA, USA
	A Practical FPGA-based Framework for Novel CMP Research Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis and Kunle Olukotun Stanford University, California, CA, USA
Dinner and Evening Panel
7:00pm	High-Level Languages for FPGAs – The Future, or a Passing Fad? Organizer: Michael Wirthlin Brigham Young University, UT, USA Misha Burich, Altera Andrew Guyler, Mentor Brian von Herzen, Rapid Prototypes Maya Gokhale, Lawrence Livermore Glenn Steiner, Xilinx

Tuesday, February 20

Session 5: Invited Session : Integrating FPGAs in High-Performance Computing
8:45am	Organizers: Paul Chow (University of Toronto) and Mike Hutton (Altera)
	High-Performance Computing Business Overview and Perspective Dan Gibbons Director, Xilinx Business Development, San Jose, CA, USA
	System, Architecture and Implementation Perspective Nathan Woods Principal Scientist, XtremeData, Schlomberg, IL, USA
	Programming Models for Parallel Systems, the Programmers Perspective Satnam Singh, Microsoft Research, Cambridge, UK
10:10am	Poster Session 3
Session 6: CAD and Architecture
11:00am	Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs Kirill Minkovich and Jason Cong University of California at Los Angeles, CA, USA
	Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams Kevin Tinmaung and Russell Tessier University of Massachusetts, Amherst, MA, USA
	GlitchLess: An Active Glitch Minimization Technique for FPGAs Julien Lamoureux, Guy Lemieux and Steven J.E. Wilton The University of British Columbia, Vancouver, Canada
12pm	Lunch
Session 7: Variation & Yield
1:30pm	Performance and Yield Enhancement of FPGAs with Within-die Variation using Multiple Configurations Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa and Hanpei Koike AIST, Japan
	Parametric Yield in FPGAs Due to Within-die Delay Variations: A Quantative Analysis Pete Sedcole and Peter Y. K. Cheung Imperial College, London, UK
	Efficient Hardware Checkpointing -- Concepts, Overhead Analysis, and Implementation Dirk Koch, Christian Haubelt and Juergen Teich University of Erlangen-Nuremberg, Germany
2:30pm	Break
Session 8: Security
2:50pm	The Shunt: An FPGA-Based Accelerator for Network Intrusion Prevention Nicholas Weaver, Vern Paxson and Jose Gonzalez ICSI, Berkeley, CA, USA
	Attacking Elliptic Curve Cryptosystems with Special-Purpose Hardware Tim Güneysu, Christof Paar and Jan Pelzl Ruhr University of Bochum, Germany
	Reconfigurable Finite Field Instruction Set Architecture Nathan Jachimiec, Fernando Martinez-Vallina and Jafar Saniie Illinois Institute of Technology, Chicago, IL, USA
3:50pm	Closing Remarks