FPGA 2006 Panel
Will Power Kill FPGAs?

For quite some time now Moore's law has allowed vendors to produce new FPGAs every two years with generally double the density, better performance, and improved features. However, there have been some new challenges. Power consumption, rarely an issue in the past, is now a limitation in many FPGA user applications. Studies have shown that FPGAs have several times the dynamic power consumption of ASICs. Moreover, static power consumption is fast becoming comparable to dynamic power in 65nm and below. Power and power measurement has been as important as performance in the FPGA "marketing wars" at 90nm, and structured ASICs have also been quick to claim power advantages.

For 90nm devices FPGA architects have responded with various solutions: multiple oxides, multiple threshold voltages, L/W optimization for power, programmable clock shut-down, and power-friendly resources. Here at the FPGA Symposium we've gone from nary a whimper five years ago to numerous paper submissions this year on low-power circuts and architectures, low-power clock networks and power-aware CAD.

But is this enough? What will happen by the time we hit 45mn? Processors have already "given up" on improving clock-rates and gone multi-core, primarily due to the power issue. Is power a looming Achilles heel for FPGAs? Will it be the issue that turns designers away from FPGAs and back to ASIC? Will new designers turn to alternative fabrics such as structured ASIC or coarse-grained to meet their power goals? Will the FPGA vendors trade all their process performance gains for power control and will this be enough to make 45nm and 32nm devices competitive? Are there new tricks that will solve the problem at these future process nodes without significant cost or performance hits? Or will the fab rescue us with new low power devices for all?

In this panel, representatives from FPGA, ASIC, structured fabric and academic perspectives will give their views on these questions and the future of logic design as it relates to power. Each panelist will give a brief summary of their views, followed by a round of questions from the audience and friendly debate.