FPGA 2006: Call for Papers

• FPGA Architecture: Novel logic block and routing architectures, combination of FPGA fabric and system blocks (processors, memories, etc.), new commercial architectures, impact of modern and future technologies (including ultra-deep submicron and nanometer scale) on the design of FPGA's (e.g. soft errors, leakage, power density, fabrication defects).
• Circuit Design for FPGAs: Novel FPGA circuits and circuit-level techniques.
• CAD for FPGAs: Placement, routing, retiming, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification, CAD for FPGA-based accelerators, CAD for incremental FPGA design and on-line design mapping and optimization.
• High-level abstractions, tools, and systems for FPGAs: General-purpose and domain-specific models, languages, tools, and techniques that facilitate the design, development, debugging, verification, and deployment of large-scale and high-performance FPGA-based applications and systems.
• FPGA-based and FPGA-like computing engines: Compiled accelerators, reconfigurable computing, adaptive computing devices, systems and software.
• Rapid-prototyping: Fast prototyping for system-level design and logic emulation.
• Applications: Innovative use of FPGAs, exploitation of FPGA features and architectures, uses of FPGAs to achieve high-performance, low-power, or high-reliability, FPGA-optimized DSP techniques, novel uses of reconfiguration, FPGA-based cores.

Authors are invited to submit English language PDF of their paper (10 pages maximum) and panel proposals by September 23, 2005. using the web interface at:

Address questions to:

André DeHon, Program Chair FPGA 2006 Dept. of CS, 256-80, CALTECH Pasadena, CA 91125 Phone : (626) 395-6569 Email : andre@cs.caltech.edu