FPGA 2001 Advance Program 2001 ACM/SIGDA Ninth International Symposium on Field Programmable Gate Arrays Doubletree Hotel, Monterey, California February 11-13, 2001 Sponsored by ACM/SIGDA with support from Altera, Xilinx, Agere Systems, Cypress and Actel Join us for the ninth ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2001), the premier forum for novel work in all areas related to FPGA technology. This year's symposium features twenty-four papers and twenty-three poster presentations describing cutting-edge FPGA research. Authors from universities, research laboratories and commercial vendors present new work on topics ranging from applications and reconfigurable computing to device architecture and design tools. An entire session is devoted to applications in image and video compression. Paper sessions are separated by ample time to peruse the poster presentations and discuss the latest FPGA news. The panel this year addresses the question of what FPGAs will look like in the era of systems-on-a-chip. Is it now clear that programmable logic should be combined with ASICs and microprocessors? How should they be combined? What tools are needed to support these devices? FPGA 2001 provides a relaxed atmosphere for informal information exchange, networking and stimulating discussions with the leaders in FPGA research and development from industry and academia as well as the next generation of FPGA researchers If you are at all interested in FPGA technology and developments, you won't want to miss this event. Organizing Committee -------------------- General Chair: Scott Hauck, U. Washington Program Chair: Martine Schlag, UCSC Publicity Chair: Russ Tessier, U. Mass.-Amherst Finance Chair: Steve Trimberger, Xilinx Program Committee ----------------- Ray Andraka, Andraka Consulting Mike Bershteyn, Quickturn Richard Cliff, Altera Jason Cong, UCLA Andre DeHon, Caltech Eugene Ding, Lucent Carl Ebeling, U. Washington Scott Hauck, U. Washington TingTing Hwang, Natl. Tsing Hua U. Sinan Kaptanoglu, Adaptive Silicon Tom Kean, Algotronix Arun Kundu, Actel Miriam Leeser, Northeastern U. Wayne Luk, Imperial College Margaret Marek-Sadowska, UCSB Jonathan Rose, U. Toronto Martine Schlag, UCSC Herman Schmit, CMU Charles Stroud, UNC-Charlotte Russ Tessier, U. Mass.-Amherst Steve Trimberger, Xilinx Steve Wilton, U. British Columbia PROGRAM ------- SUNDAY, FEBRUARY 11, 2001 6:00PM Registration 7:00PM Welcoming Reception MONDAY, FEBRUARY 12, 2001 7:30AM Continental Breakfast and Registration 8:20AM Opening remarks: Scott Hauck, Martine Schlag Session 1. Placement and Routing Chair: Carl Ebeling, University of Washington 8:30AM Timing-Driven Placement for Hierarchical Programmable Logic Devices. Michael Hutton, Khosrow Adibasmii and Andrew Leaver, Altera. 8:50AM LRoute: A Delay Minimal Router for Hierarchical CPLDs. K.K. Lee, Synopsys; Martin D.F. Wong, Univerity of Texas at Austin. 9:10AM A Crosstalk-Aware Timing-Driven Router for FPGAs. Steven J.E. Wilton, University of British Columbia. 9:30AM Runtime and Quality Tradeoffs in FPGA Placement and Routing. Chandra Mulpuri and Scott Hauck, University of Washington. 9:50AM Coffee Break and Poster Presentations. Session 2. Technology Mapping Chair: Steven Wilton, University of British Columbia 10:50AM Performance-Driven Mapping for CPLD Architectures. Deming Chen, Jason Cong, Milos Ercegovac and Zhijun Huang, University of California, Los Angeles. 11:10AM Simultaneous Logic Decomposition with Technology Mapping in FPGA Designs. Gang Chen and Jason Cong, University of California, Los Angeles. 11:30AM Poster Presentations. 12:00PM Lunch Session 3. Routing Architectures Chair: Tom Kean, Algotronix 1:30PM Using Sparse Crossbars within LUT Clusters. Guy G. Lemieux and David M. Lewis, University of Toronto. 1:50PM Detailed Routing Architectures for Embedded Programmable Logic IP Cores. Peter Hallschmid and Steven J.E. Wilton, University of British Columbia. 2:10PM Mixing Buffers and Pass Transistors in FPGA Routing Architectures. Mike Sheng and Jonathan Rose, University of Toronto. 2:30PM Coffee Break and Poster Presentations. Session 4. Applications Chair: Ray Andraka, Andraka Consulting 3:30PM Reprogrammable Network Packet Processing on the Field Programmable Port Extender (FPX). John W. Lockwood, Naji Naufel, David E. Taylor and Jon S. Turner, Washington University. 3:50PM Fast Implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. Pawel Chodowiec, Po Khuon, and Kris Gaj, George Mason University. 4:10PM Algorithmic Transformations in the Implementation of K-means Clustering on Reconfigurable Hardware. Mike Estlick, Miriam Leeser, Northeastern University; John J. Szymanski, James Theiler, Los Alamos National Laboratory. 6:00PM Dinner 7:30PM Panel: Is marriage in the cards for programmable logic, microprocessors and ASICs? Moderator: Sinan Kaptanoglu, Adaptive Silicon Panelists: John East, Actel, Tim Garverick, Adaptive Silicon, Scott Hauck, University of Washington, Danesh Tavana, Triscend, Steve Trimberger, Xilinx, Ronnie Vasishta, LSI Logic. (Additional panelists to be announced) The panelists focus on the possibility, likelihood or inevitability of combinations of programmable logic, microprocessors and ASICs in a single chip. Will they be as general as possible or application specific? Will all three types of logic be involved or perhaps only two? How much of the die area should be allocated to programmable logic? How will the CAD tools cope with the speed mismatch between the programmable logic and fixed logic on the same chip? How will the designs be partitioned into programmable and parts; will it be done by humans or by CAD tools? These future predictions may depend on the system design size. Are the answers for 500K gate system designs different from those for 5,000K gate system designs? What will happen when 50,000K gate system designs become commonplace in 5 years? TUESDAY, FEBRUARY 13, 2001 7:30AM Continental Breakfast and Registration Session 5. Reconfigurable Computing Chair: Steve Trimberger, Xilinx 8:30AM Attacking the Semantic Gap Between Application Programming Languages and Configurable Hardware. Greg Snider, Barry Shackleford and Richard J. Carter, Hewlett-Packard Laboratories. 8:50AM Matching and Searching Analysis for Parallel Hardware Implementation on FPGAs. Pablo Moisset, Pedro Diniz and Joonseok Park, University of Southern California/Information Sciences Institute. 9:10AM Evaluation of the Streams-C C-to-FPGA Compiler: An Applications Perspective. Janette Frigo, Maya Gokhale and Dominique Lavenier, Los Alamos National Laboratory. 9:30AM The Effect of Reconfigurable Units in Superscalar Processors. Jorge E. Carrillo E. and Paul Chow, University of Toronto. 9:50AM Coffee Break and Poster Presentations. Session 6. Pipelined Routing Architectures Chair: Andre DeHon, Cal Tech 10:50AM Interconnect Pipelining in a Throughput-Intensive FPGA Architecture. Amit Singh, Arindam Mukherjee and Malgorzata Marek-Sadowska, University of California, Santa Barbara. 11:10AM The Case for Registered Routing Switches in Field Programmable Gate Arrays. Deshanand P. Singh and Stephen D. Brown. University of Toronto. 11:30AM Poster Presentations. 12:00PM Lunch Session 7. Issues in FPGA-based Systems Chair: Chuck Stroud, University of North Carolina - Charlotte 1:30PM Configuration Compression for FPGA-based Embedded Systems. Andreas Dandalis and Viktor K. Prasanna, University of Southern California. 1:50PM A Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations. Wei-Je Huang and Edward J. McCluskey, Stanford University. 2:10PM Run-Time Defect Tolerance using JBits. Prasanna Sundararajan and Steven A. Guccione, Xilinx. 2:30PM Coffee Break and Poster Presentations. Session 8. Applications in Image/Video Compression Chair: Miriam Leeser, Northeastern University 3:30PM A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. Jörg Ritter and Paul Molitor, Martin-Luther-University. 3:50PM An FPGA-Based Video Compressor for H.263 Compatible Bitstreams. G. Lienhart, R. Lay, K.H. Noffz and R. Männer, University of Mannheim. 4:10PM FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. S. Ramachandran and S. Srinivasan, Indian Institute of Technology, Chennai. 4:30PM Closing Remarks: Scott Hauck, Martine Schlag General Information About Monterey About Monterey: The Monterey Peninsula is famous for its many attractions and recreational activities, such as John Steinbeck's famous Cannery Row and the Monterey Bay Aquarium. Also, play one of the 19 championship golf courses. Charter fishing is available right at Fisherman's Wharf. Monterey is renowned worldwide for its spectacular coastlines, including Big Sur and the 17-Mile drive. Shopping opportunities and restaurants abound, and the hotel can organize visits to Carmel-by-the-Sea, Cannery Row, and other area sites. Recreational activities available to all hotel guests include swimming pool, Jacuzzi, land and sea recreational rental equipment (kayaking, rollerblading, bicycling and snorkeling). Directions to the Doubletree from Monterey Airport: Take Highway 68 to the Monterey Fisherman's Wharf exit. At the first light turn right onto Aguajito. Continue on Aguajito until it ends at Del Monte. Make a left onto Del Monte and continue for three lights. At the third light get in the left turn lane to continue straight on Del Monte to the Hotel. >From San Francisco International and San Jose International Airports: Take Highway 101 South to Route 156. Travel on Route 156 West to Highway 1 South to the Del Monte/Pacific Grove exit. Proceed on Del Monte through 7 lights to Alvarado. (*At the 5th light--McDonald's on left--stay in the left lane in order to continue straight on Del Monte.) At Alvarado, turn right into the Doubletree entrance. >From the South/Carmel on Highway One: Take the Aguajito exit. Turn left at the first light. Continue on Aguajito until it ends at Del Monte. Make a left and continue straight for three lights, then get in the left turn lane to continue straight on Del Monte to Doubletree. Hotel Parking: Self-parking for hotel guests is $10 per day, with in and out privileges; $12 per day for valet parking. For those who are not staying at the hotel there is cheaper parking a block away from the hotel in a parking garage. HOTEL INFORMATION AND RESERVATION FORM Doubletree Hotel, Monterey, California: ACM/FPGA 2001, February 11-13, 2001. Name (first middle last):_______________________Date of arrival:______________ Time of Arrival:______________________Departure Date:_________________ Name(s) of additional person(s) sharing room:________________________________ Credit Card Type:______Expiration Date:______Credit Card Number:_______________ Mailing Address:_____________________________________________________________ _____________________________________________________________________________ Phone: (____) _____________ Hotel Rates: (please check all that apply) _____Single Occupancy - $139 ________Double Occupancy - $139 _____Non-Smoking ________Additional Person per night - $20 per night Rates are subject to 10% occupancy tax per night, per room. Please enclose one night's deposit or complete credit card information. The deposit is refundable up to 48 hours before the symposium with the cancellation notice. Check-in time is after 3:00 PM / Check-out time is 12 noon. Reservations must be received by January 17, 2001. Reservations received after this date are based upon availability. Please return this form directly to: Attn: Reservations Department Doubletree Hotel Monterey 2 Portola Plaza Monterey, CA 93940. Or you can make reservations directly with the Hotel at (831) 649-4511, or at Doubletree Reservations office at (800) 222-TREE. Be sure to identify yourself as an ACM FPGA 2001 Conference Attendee. /http://www.hilton.com/doubletree/hotels/MRYADDT/index.html REGISTRATION FORM FOR FPGA'01 Ninth ACM International Symposium on Field-Programmable Gate Arrays February 11-13, 2001 Monterey, California First Name for Badge:__________________________________________________________ Name (first,middle,last):______________________________________________________ Affiliation (for badge):_______________________________________________________ Title/Job Function:____________________________________________________________ Address:_______________________________________________________________________ City:______________________ State:_____________________ Zip Code:______________ Country:___________________ Email:____________________________________________ Phone: (____)________________________ Fax: (_____)_____________________________ ACM/SIG Member ID:_______________________ Student ID:______________________ Special Needs:_______________________ Special Meal Requirements: Vegetarian Kosher Vegan Do not include my name, address and e-mail id in the conference attendee listing _____. PLEASE NOTE Conference registration fee includes one copy of the conference proceedings, breakfast, lunch, Sunday Reception, and Monday Banquet. REGISTRATION FEES (Please circle appropriate fees) The cut off date for preregistration is February 2,2001. After this date you must register on-site. Registration on or before 1/19/01 Member Non-Member Student FPGA Conference $325.00 $425.00 $ 85.00 Registration after 1/19/01 Member Non-Member Student FPGA Conference $400.00 $500.00 $ 95.00 Guest Banquet Tickets: ____ tickets x $60 = ______ Membership: SIGDA Membership $ 15 Student SIGDA Membership $ 15 ACM Membership $ 95 ACM Student Membership $ 38 Please check the ACM website for other options including proceedings packages and digital library. Total Fees: US $_______________________ (Make checks payable to ACM/FPGA'01 Conference) Payment included (circle one): American Express Master Card Visa Check Credit Card Number:_____________________ Expiration Date:__________________ Names as it appears on Credit Card:________________________________________ Signature:_________________________________________________________________ For questions (8:30 am - 4:30 PM EST) Email: acmhelp@acm.org. For Credit Card payments, Fax 1-212-944-1318 Telephone: (US and Canada) 1-212-342-6626, (outside the US) 1-212-626-0500. If paying by check, mail check with registration form to: ACM Member Services P.O. Box 11405 New York, NY 10286-1405, USA Cancellations must be received in writing by contacting the ACM Member Services Department. A US $50 cancellation fee will be charged. You should receive e-mail confirmation within 3 business days. If you do not please contact our member services department at the above contact information.